(1) Field of the Invention
The present invention relates to a method of fabricating a metal oxide semiconductor field effect transistor, (MOSFET), device, and more specifically to a process used to create a buried contact feature, for the MOSFET device.
(2) Description of Prior Art
The semiconductor industry is continually striving to improve the performance of MOSFET devices, while still attempting to maintain, or even to reduce the cost of manufacturing MOSFET devices. These objectives have been successfully addressed via micro-miniaturization, or the ability of the semiconductor manufacturing community to fabricate MOSFET devices with sub-micron features. The smaller features result in decreases in performance robbing, parasitic capacitances, as well as decreases in performance degrading resistances. In addition the sub-micron features allow comparable logic and memory functions to be obtained on smaller semiconductor chips, thus resulting in more semiconductor chips per starting substrate, thus reducing the cost of a specific MOSFET chip. Several semiconductor fabrication disciplines, such as photolithography and dry etching, have contributed to the trend to micro-miniaturization. For example the use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have made the attainment of sub-micron images in photoresist layers, routine. In addition the development of more advanced dry etching tools have allowed the sub-micron images in photoresist layers to be successfully transferred to underlying materials, used for the fabrication of MOSFET devices.
In addition to the advances in specific fabrication disciplines, contributing to the attainment of sub-micron MOSFET devices, specific MOSFET structural developments have also played a role in successfully creating sub-micron MOSFET devices. For example the ability to contact the source and drain region of the MOSFET device, outside the active device region, has resulted in smaller MOSFET devices, thus creating higher performing and less expensive devices. The use of a buried contact process, featuring the placement of a doped region, adjacent to a source and drain region, and contacting this region via a polysilicon layer, has allowed the active device region of the MOSFET device to be decreased. The amount of area allotted to a buried contact region has to be minimized to satisfy the high density design objectives for static random access memory, (SRAM), designs. However the amount of contact area, between an underlying buried contact region, and an overlying contact layer, has to adequate, to avoid resistance problems, that can result in performance degradation.
This invention will present a process for increasing the contact area between a buried contact structure, and an overlying contact layer, by removing a portion of insulator, from an insulator filled, shallow trench, during the buried contact patterning process, followed by an angled, buried contact, ion implantation procedure, used to create the buried contact region. Subsequent polysilicon deposition, and patterning, creates a buried contact structure, to a buried contact region, in which the buried contact region is comprised of a region formed in the top surface of the semiconductor substrate, as well as a region of buried contact, formed on the sides of the semiconductor substrate, exposed in the shallow trench. Prior art, such as Huang, U.S. Pat. No. 5,607,881, describe a process of forming a crevice in the semiconductor substrate, followed by ion implantation of the buried contact spices, in the creviced region. However that prior art does not use a side of a shallow trench, for the increased surface area, nor does that prior art employ the angled ion implantation procedure, for formation of a buried contact region, on the exposed sides of the semiconductor substrate.